1. Field of the Invention
The present invention relates to semiconductor devices in general and, more particularly to a method and apparatus for reducing noise between lead fingers by providing an electrically isolated no-connect (“NC”) lead in the lead frame.
2. Background of Related Art
Well known types of semiconductor devices are connected to a component known as lead frames and subsequently encapsulated in plastic for use in a wide variety of applications. The lead frame is typically formed from a single, continuous sheet of metal, typically by metal stamping or chemical etching operations. A “conventional” lead frame usually includes an outer supporting frame, a central semiconductor device support pad (paddle), and a plurality of lead fingers, each lead finger having, in turn, a terminal bonding portion near the central semiconductor device supporting pad. In the assembly of semiconductor devices utilizing such lead frames, a semiconductor device in the form of a semiconductor die, or integrated circuit (IC) is secured to the central supporting pad, a paddle (such as by a solder or epoxy die-attach, although a double-sided adhesive tape-type attach has also been suggested in the art). Some of the lead fingers carry a signal to the semiconductor device, while others provide a power source or a ground. The lead fingers are electrically connected to bond pads on the semiconductor device using fine wires, termed “bond wires.” In a conventional wire bonding process, the bond wires are formed and bonded, one at a time, between each bond pad on the semiconductor device and an associated lead finger of the lead frame. After the wire bonds between the contact pads of the semiconductor device and the lead fingers are made, the semiconductor device and wire bonds are typically encapsulated in plastic using a transfer or injection molding process. Finally, the rails of the outer supporting frame of the lead frame are removed leaving portions of the lead fingers extending beyond the encapsulated semiconductor device, the lead fingers being simultaneously formed to a finished shape in a so-called “trim and form” operation.
One common variation on the foregoing arrangement is to eliminate the die support pad or paddle and adhesively attach the semiconductor device to the lead fingers of the lead frame using an alpha barrier, such as a polyimide tape, for example, KAPTON™ tape. In such an arrangement, a so-called “leads-over-chip” arrangement (LOC), a plurality of lead fingers extend over the active surface of a semiconductor device toward one or more lines of bond pads, wherein bond wires make the electrical connection between the lead fingers and the bond pads. Examples of such LOC configurations are shown in U.S. Pat. No. 4,862,245 to Pashby and U.S. Pat. No. 5,286,679 to Farnworth et al., the latter being assigned to the assignee of the present invention.
A semiconductor device and lead frame configuration of one prior art semiconductor device assembly 10 is illustrated in drawings FIG. 1A and FIG. 1B. As shown, the semiconductor device 14 is supported by tape 16. A lead frame 12 typically has a pattern of lead fingers 18. Conductive wires 22 connect the lead fingers 18 to the bond pads 24 on the active surface 35 of the semiconductor device 14. Following wire bonding, the semiconductor device 14 and lead frame 12 are encapsulated, typically with a polymeric or ceramic material, to form a package. The connecting segments 34 between the lead fingers 18 are cut away and trimmed to singulate each lead finger 18, the outer portion of the lead finger 18 ultimately configured as a pin for attachment to a host electronic apparatus, not shown.
The lead frame 12 is one of a plurality that is connected in end-to-end fashion, thereby forming a strip of lead frames, the plurality referred to as a lead frame strip. Lead frame 12 is positioned between a preceding frame 11 and a following frame 13. Typically, following encapsulation, the lead frames 11, 12 and following frame 13 are separated one from the other and the opposing edges or rails 15 and 17 are removed so that each frame with a semiconductor device attached thereto becomes a separate and useable semiconductor device assembly.
The leads 18 may be conventionally designated in the lead register for a memory device as power supply voltage VCC, reference voltage VSS, data input DIN, data output DOUT, write enable signal WE, row address strobe RAS, address signal A, column address strobe CAS, output enable OE, and other labels as required. The particular labels designated in the lead register may differ from manufacturer to manufacturer and differ depending upon the use to which the device is applied.
In order to lower their overall cost, semiconductor device assemblies 10 are typically made to be used in a variety of applications, and in most applications, only some of the leads 18 are used. This is particularly true of the address signal A leads. Thus, while some leads 18, such as VCC, VSS, DIN, DOUT and WE, may be used in all or nearly all applications, only some of the address signal (A) leads are typically used, leaving some leads as unused, no-connect, or “NC” leads.
The leads most prone to causing induction noise, i.e., Vcc, Vss, DIN, DOUT and WE, are conventionally located to minimize inductive interaction with the address signal A leads. The leads generally most subject to induction effects are those designated as VCC, VSS, DIN, DOUT, WE, RAS, and CAS.
As the capacity and speed of many integrated circuit devices such as dynamic random access memories (DRAMs) have increased, the number of inputs and outputs (I/Os) to each die has increased, requiring more numerous and complex external connections thereto. In some instances, this requires undesirably long lead frame lead fingers (as depicted in the lead frame 12 of FIG. 1) to place the lead ends in contact with, or in close proximity to, the bond pads serving as inputs and outputs or I/Os, for the typical die.
While lead inductance in IC packages has not traditionally been troublesome because slow signal frequencies of past devices render the effects of such inductance relatively insignificant, faster and ever-increasing signal frequencies of state-of-the-art electronic systems have substantially increased the practical significance of lead inductance. For example, at such faster signal frequencies, performance of IC dice using lead frames for external electrical connection is slower than desirable because the inductance associated with the lead fingers slows changes in signal currents through the leads, prolonging signal propagation through the leads. Further, digital signals propagating along the lead fingers are dispersing or “spreading out,” because the so-called “Fourier” components of various frequencies making up the digital signals propagate through the inductance associated with the lead fingers at different speeds, causing the signal components, and thus the signals themselves, to disperse along the lead fingers. While mild dispersion merely widens the digital signals without detrimental effect, severe dispersion can make the digital signals unrecognizable upon receipt. In addition, so-called “reflection” signals propagating along the lead fingers as a result of impedance mismatches between the lead fingers and associated IC die or between the lead fingers and external circuitry, caused in part by lead-associated inductance, can distort normal signals propagating along the lead fingers concurrently with the reflection signals. Further, magnetic fields created by signal currents propagating through the lead-associated inductance can induce currents in adjacent lead fingers, causing so-called “crosstalk” noise on the latter. While these various effects might be troublesome in any electronic system, the aforementioned trend toward lower voltage systems (currently 3.3 volts) and away from the traditional 5.0 volt systems increases their visibility and significance.
At state-of-the art operational speeds, signal propagation delays, switching noise, and crosstalk between signal conductors resulting from mutual inductance and self inductance phenomena of the conductive paths all become significant to signal degradation. Mutual inductance results from an interaction between magnetic fields created by signal currents flowing to and from a lead frame-mounted, packaged IC die through the leads or “lead fingers,” while self inductance results from the interaction of the foregoing fields with magnetic fields created by oppositely-directed currents flowing to and from ground.
Certain currently-popular die and package configurations serve to exacerbate the noise problems by favoring use of a large plurality of laterally adjacent lead fingers of substantial length. For example, the aforementioned LOC configurations typically place the bond pads of a die in one or two rows extending along the central, longitudinal axis of the die. To accommodate the centralized bond pad location for wire-bonding and at the same time eliminate the need for a conventional die-attach paddle as a physical die support, LOC lead frames have been developed that employ lead fingers extending from the sides of the die and over the active surface into close proximity with the bond pad row or rows.
While a mechanically desirable packaging concept, the LOC-type long, mutually parallel lead finger runs over the active surface becoming abusive in terms of unacceptably increasing real impedance as well as lead inductance (both self and mutual) in the circuit. These lead finger runs also increase signal reflection in the circuit due to transmission line effects and degrade signal integrity due to the aforementioned propagation delays, switching noise, and crosstalk.
LOC configurations are merely one example of the type of packaging promoting the above-referenced undesirable noise phenomena. However, the same undesirable characteristics may be experienced with other lead frame configurations employing extended lead fingers, particularly large groups of such lead fingers in close mutual proximity. Such configurations include a lead frame with a paddle, lead-under-chip (LUC) configurations, and configurations wherein a large number of leads extend from several sides of a semiconductor die to a single side or edge of a package, such as in a vertical surface mount package, or VSMP.
Packages have previously been configured in an attempt to reduce package noise of the type described above. For example, the primary factors affecting crosstalk include the surface area of the signal line directed to an adjacent signal line, the signal line length being a factor of the surface area, the distance between the signal lines and the dielectric constant (∈r) of the material between the signal lines. Therefore, increasing the distance between the signal lines, or lead fingers is one way to reduce crosstalk. As illustrated in FIG. 2, if spaces 5 are permitted between adjacent lead fingers in an arrangement where the lead fingers 4 are adhered to the active surface of a semiconductor die 1, the application pressure applied on the tape 2 decreases substantially in the spaces 5 with the result that the tape 2 peels off from the semiconductor die 1 along the spaces 5 during the die attach step. The peeling off of the tape 2 makes the lead fingers 4 unstable on the surface of the semiconductor die 1, and may degrade the reliability of the semiconductor die 1. The gap 6 formed between the tape 2 and semiconductor die 1 may develop a trapped air pocket in the subsequent molding of the package body. The trapped air pockets may cause crack propagation and delamination of the package body.
The peeling off of the adhesive tape may be prevented by providing a no-connect lead finger (NC lead). This no-connect lead finger is not required for a connection, but extends into the package body like adjacent leads. The NC lead adds an additional solder connection for strengthening package attachment to a printed circuit board, however voltages are often routed through a pad on the printed circuit board to which the NC lead is soldered. The NC lead, as a consequence, becomes charged and can itself become a source of noise for adjacent leads.
Accordingly, the inventor has recognized the need for a low-cost, reduced-inductance circuit configuration adaptable to current packaging designs and employing conventional and readily available materials, equipment and fabrication techniques.